View SCC2691_35225.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
SCC2691 Universal asynchronous receiver/transmitter (UART)
Product specification Supersedes data of 1995 May 01 IC19 Data Handbook 1998 Sep 04
Philips Semiconductors
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
DESCRIPTION
The Philips Semiconductors SCC2691 Universal Asynchronous Receiver/Transmitter (UART) is a single-chip CMOS-LSI communications device that provides a full-duplex asynchronous receiver/transmitter. It is fabricated with Philips Semiconductors CMOS technology which combines the benefits of high density and low power consumption. The operating speed of the receiver and transmitter can be selected independently as one of 18 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the UART particularly attractive for dual-speed channel applications such as clustered terminal systems. The receiver is quadruple buffered to minimize the potential of receiver overrun or to reduce interrupt overhead in interrupt driven systems. In addition, a handshaking capability is provided to disable a remote UART transmitter when the receiver buffer is full. The UART provides a power-down mode in which the oscillator is frozen but the register contents are stored. This results in reduced power consumption on the order of several magnitudes. The UART is fully TTL compatible and operates from a single +5V power supply.
PIN CONFIGURATIONS
RDN RxD TxD MPO MPI A2 A1 A0 X1/CLK X2 RESET 1 2 3 4 5 6 7 8 9 10 11 N24 AND D24 PACKAGES 24 23 22 21 20 19 18 17 16 15 14 13 VCC WRN D0 D1 D2 D3 D4 D5 D6 D7 CEN INTRN
GND 12
4
1
26
5 A28 PACKAGE
25
FEATURES
11 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VCC RDN RxD TxD MPO MPI NC NC A2 A1 A0 X1/CLK X2 RESET Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 18
19
* Full-duplex asynchronous receiver/transmitter * Quadruple buffered receiver data register * Programmable data format:
- 5 to 8 data bits plus parity - Odd, even, no parity or force parity - 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
Symbol GND INTRN CEN D7 D6 D5 D4 D3 NC D2 D1 NC D0 WRN
* 16-bit programmable Counter/Timer * Baud rate for the receiver and transmitter selectable from:
- 22 fixed rates: 50 to 115.2K baud - Non-standard rates to 115.2kb - Non-standard user-defined rate derived from programmable timer/ counter - External 1X or 16X clock
SD00122
Figure 1. Pin Configurations
* Single interrupt output with seven maskable interrupting
conditions
* Parity, framing, and overrun detection * False start bit detection * Line break detection and generation * Programmable channel mode
- Normal (full-duplex) - Automatic echo - Local loopback - Remote Loopback
* On-chip crystal oscillator * Low power mode * TTL compatible * Single +5V power supply * Commercial (0C to +70C) and industrial (-40C to +85C)
temperature versions available
* SOL, PLCC and 300 mil wide DIP packages available
* Multi-function programmable 16-bit counter/timer
1998 Sep 04
2
853-1078 19971
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
ORDERING INFORMATION
COMMERCIAL PACKAGES 24-Pin Plastic Dual In-Line Package (DIP) 28-Pin Plastic Leaded Chip Carrier (PLCC) Package 24-Pin Plastic Small Outline Large (SOL) Package VCC = +5V +10%, TA = 0C to +70C SCC2691AC1N24 SCC2691AC1A28 SCC2691AC1D24 INDUSTRIAL VCC = +5V +10%, TA = -40C to +85C SCC2691AE1N24 SCC2691AE1A28 DWG # SOT222-1 SOT261-3 SOT137-1
BLOCK DIAGRAM
INTERNAL DATA BUS 8 D0-D7 BUS BUFFER CHANNEL A TRANSMIT HOLDING REG TRANSMIT SHIFT REGISTER RECEIVE HOLDING REG (3) RxD INTERRUPT CONTROL IMR INTRN ISR RECEIVE SHIFT REGISTER MR1, 2 CR SR TxD
RDN WRN CEN A0-A2 RESET 3
OPERATION CONTROL ADDRESS DECODE R/W CONTROL CONTROL
TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER CRYSTAL OSCILLATOR POWER DOWN LOGIC X1/CLK CSR X2 ACR CTUR CTLR
TIMING
INPUT PIN CHANGE OF STATE DETECTOR MPI
OUTPUT PIN FUNCTION SELECT LOGIC ACR
MPO
VCC GND
SD00123
Figure 2. Block Diagram
1998 Sep 04
3
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
PIN DESCRIPTION
MNEMONIC D0-D7 PIN NO. DIP 22-15 PLCC 27, 25, 24, 22-18 17 TYPE I NAME AND FUNCTION Data Bus: Active-high 8-bit bidirectional 3-State data bus. Bit 0 is the LSB and bit 7 is the MSB. All data, command, and status transfers between the CPU and the UART take place over this bus. The direction of the transfer is controlled by the WRN and RDN inputs when the CEN input is low. When the CEN input is high, the data bus is in the 3-State condition. Chip Enable: Active-low input. When low, data transfers between the CPU and the UART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A2 inputs. When CEN is high, the UART is effectively isolated from the data bus and D0-D7 are placed in the 3-State condition. Write Strobe: Active-low input. A low on this pin while CEN is low causes the contents of the data bus to be transferred to the register selected by A0-A2. The transfer occurs on the trailing (rising) edge of the signal. Read Strobe: Active-low input. A low on this pin while CEN is low causes the contents of the register selected by A0-A2 to be placed on the data bus. The read cycle begins on the leading (falling) edge of RDN. Address Inputs: Active-high address inputs to select the UART registers for read/write operations. Reset: Master reset. A high on this pin clears the status register (SR), the interrupt mask register (IMR), and the interrupt status register (ISR), sets the mode register pointer to MR1, and places the receiver and transmitter in the inactive state causing the TxD output to go to the marking (high) state. Clears Test modes. Interrupt Request: This active-low output is asserted upon occurrence of one or more of seven maskable interrupting conditions. The CPU can read the interrupt status register to determine the interrupting condition(s). This open-drain output requires a pull-up resistor. Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing. Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it is permissible to ground it. Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is specified, this input is sampled on the rising edge of the clock. Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the marking (high) condition when the transmitter is idle or disabled and when the UART is operating in local loopback mode. If external transmitter is specified, the data is shifted on the falling edge of the transmitter clock. Multi-Purpose Output: One of the following functions can be selected for this output pin by programming the auxiliary control register: RTSN - Request to send active-low output. This output is asserted and negated via the command register. By appropriate programming of the mode registers, RTSN can be programmed to be automatically reset after the character in the transmitter is completely shifted or when the receiver FIFO and shift register are full. C/TO - The counter/timer output. TxC1X - The 1X clock for the transmitter. TxC16X - The 16X clock for the transmitter. RxC1X - The 1X clock for the receiver. RxC16X - The 16X clock for the receiver. TxRDY - The transmitter holding register empty signal. Active-low output. (Open drain) RxRDY/FFULL - The receiver FIFO not empty/full signal. Active-low output. (Open drain) Multi-Purpose Input: This pin can serve as an input for one of the following functions: GPI - General purpose input. The current state of the pin can be determined by reading the ISR. CTSN - Clear-to-send active-low input. CTCLK - Counter/timer external clock input. RTCLK - Receiver and/or transmitter external clock input. This may be a 1X or 16X clock as programmed by CSR[3:0] or CSR[7:4]. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Power Supply: +5V supply input. Ground
CEN
14
I
WRN
23
28
I
RDN
1
2
I
A0-A2 RESET
8-6 11
11-9 14
I I
INTRN
13
16
O
X1/CLK
9
12
I
X2 RxD TxD
10 2 3
13 3 4
I I O
MPO
4
5
O
MPI
5
6
I
VCC GND
24 12
1 15
I I
1998 Sep 04
4
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
ABSOLUTE MAXIMUM RATINGS1
SYMBOL TA TSTG VCC VS PD PARAMETER Operating ambient temperature range2 Storage temperature range Voltage from VCC to GND3 Voltage from any pin to Power Dissipation ground3 RATING Note 4 -65 to +150 -0.5 to + 7.0 -0.5 to VCC +10% 300 UNIT C C V V mW
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperature, the device must be derated based on +150C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and VCC supply range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
SYMBOL VIL VIH PARAMETER Input low voltage Input high voltage All except X1/CLK X1/CLK VOL VOH4 IIL ILL IOD IXIL IXIH IX2L IX2H ICCA Output low voltage Output high voltage (except open drain outputs) Input leakage current Data bus 3-State leakage current Open-drain output leakage current X1/CLK low input current X1/CLK high input current X2 low output current X2 high output current Power supply current, active IOL = 2.4mA IOH = -400A VIN = 0 to VCC VO = 0.4 to VCC VO = 0.4 to VCC VIN = 0, X2 floated VIN = VCC, X2 floated VOUT = 0, X1/CLK = VCC VOUT = VCC, X1/CLK = 0V 0C to +70C -40C to +85C 0.8 1.0 2.4 -10 -10 -10 -100 0 -100 100 2.0 2.5 500 -30 30 10 10 10 0 100 2 0.8VCC TEST CONDITIONS LIMITS Min Typ Max 0.8 UNIT V V V V V A A A A A A A mA mA A
VCC 0.4
ICCD Power down current5 NOTES: 1. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and VCC supply range. 2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of 20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and output voltages of 0.8V and 2V as appropriate. 3. Typical values are at +25C, typical supply voltages, and typical processing parameters. 4. Test condition for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7k to VCC. 5. For power down current levels in the 1A region see the UART application note.
1998 Sep 04
5
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
SYMBOL Reset timing (Figure 3) tRES Reset pulse width Bus timing (Figure 4)5 tAS A0-A2 setup time to RDN, WRN low tAH A0-A2 hold time from RDN, WRN low tCS CEN setup time to RDN, WRN low tCH CEN hold time from RDN, WRN high tRW WRN, RDN pulse width tDD Data valid after RDN low tDF Data bus floating after RDN high tDS Data setup time before WRN high tDH Data hold time after WRN high tRWD Time between reads and/or writes6, 7 MPI and MPO timing (Figure 5)5 tPS MPI input setup time before RDN low tPH MI input hold time after RDN low tPD MPO output valid after WRN high Interrupt timing (Figure 6) INTRN negated Read RHR (RxRDY/FFULL interrupt) Write THR (TxRDY, TxEMT interrupt) Reset command (break change interrupt) Reset command (MPI change interrupt) Stop C/T command (counter interrupt) Write IMR (clear of interrupt mask bit) Clock timing (Figure 7) tCLK fCLK9 tCTC fCTC8 tRX fRX8 tTX fTX8 X1/CLK high or low time X1/CLK frequency Counter/timer clock high or low time Counter/timer clock frequency RxC high or low time RxC frequency (16X) RxC frequency (1X) TxC high or low time TxC frequency (16X) TxC frequency (1X) 100 0 100 0 220 0 0 220 0 0 tIR 100 10 100 0 0 150 125 110 50 30 150 30 30 370 ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER LIMITS Min Typ Max UNIT
370 370 370 370 370 270
ns ns ns ns ns ns ns MHz ns MHz ns MHz MHz ns MHz MHz ns ns
4.0 4.0 3.6864 2.0 1.0 2.0 1.0 350 150
Transmitter timing (Figure 8) tTXD TxD output delay from TxC external clock input on IP pin tTCS Output delay from TxC low at OP pin to TxD data output Receiver timing (Figure 9) 0
tRXS RxD data setup time before RxC high at external clock input on IP pin 100 ns tRXH RxD data hold time after RxC high at external clock input on IP pin 100 ns NOTES: 1. Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and VCC supply range. 2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of 20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and output voltages of 0.8V and 2V as appropriate. 3. Typical values are at +25C, typical supply voltages, and typical processing parameters. 4. Test condition for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7k to VCC. 5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the `strobing' input. In this case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are ORed internally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. If CEN is used as the `strobing' input, this parameter defines the minimum high time between one CEN and the next. The RDN signal must be negated for tRWD guarantee that any status register changes are valid. 7. Consecutive write operations to the command register require at least three rising edges of the X1 clock between writes. 8. These parameters are guaranteed by design, but are not 100% tested in production. 9. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz. 1998 Sep 04 6
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
BLOCK DIAGRAM
As shown in the block diagram, the UART consists of: data bus buffer, interrupt control, operation control, timing, receiver and transmitter.
SCC2692, SCC68681 and SCC2698B" Philips Semiconductors ICs for Data Communications, IC-19, 1994.
Mode registers 1 and 2 are accessed via an auxiliary pointer. The pointer is set to MR1 by RESET or by issuing a reset pointer command via the command register. Any read or write of the mode register while the pointer is at MR1 switches the pointer to MR2. the pointer then remains at MR2 so that subsequent accesses are to MR2, unless the pointer is reset to MR1 as described above.
Data Bus Buffer
The data bus buffer provides the interface between the external and internal data busses. It is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and UART.
Interrupt Control
A single interrupt output (INTRN) is provided which may be asserted upon occurrence of any of the following internal events: - Transmit holding register ready - Transmit shift register empty - Receive holding register ready or FIFO full - Change in break received status - Counter reached terminal count - Change in MPI input - Assertion of MPI input Associated with the interrupt system are the interrupt mask register (IMR) and the interrupt status register (ISR). The IMR can be programmed to select only certain of the above conditions to cause INTRN to be asserted. The ISR can be read by the CPU to determine all currently active interrupting conditions. However, the bits of the ISR are not masked by the IMR.
Timing Circuits
The timing block consists of a crystal oscillator, a baud rate generator, a programmable 16-bit counter/timer, and two clock selectors. The crystal oscillator operates directly from a 3.6864MHz crystal connected across the X1/ CLK and X2 inputs with a minimum of external components. If an external clock of the appropriate frequency is available, it may be connected to X1/CLK. If an external clock is used instead of a crystal, X1/CLK is driven using a configuration similar to the one in Figure 7. In this case, the input high-voltage must be capable of attaining the voltage specified in the DC Electrical Characteristics. The clock serves as the basic timing reference for the baud rate generator (BRG), the counter/timer, and other internal circuits. A clock frequency, within the limits specified in the electrical specifications, must be supplied if the internal BRG is not used. The baud rate generator operates from the oscillator or external clock input and is capable of generating 18 commonly used data communications baud rates ranging from 50 to 38.4K baud. Thirteen of these are available simultaneously for use by the receiver and transmitter. Eight are fixed, and one of two sets of five can be selected by programming ACR[7]. The clock outputs from the BRG are at 16X the actual baud rate. The counter/timer can be used as a timer to produce a 16X clock for any other baud rate by counting down the crystal clock or an external clock. The clock selectors allow the independent selection by the receiver and transmitter of any of these baud rates or an external timing signal.
Operation Control
The operation control logic receives operation commands from the CPU and generates appropriate signals to internal sections to control device operation. It contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus buffer. The functions performed by the CPU read and write operations are shown in Table 1.
Table 1.
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Register Addressing
A0 0 1 0 1 0 1 0 1 READ (RDN = 0) MR1, MR2 SR BRG Test RHR 1X/16X Test ISR CTU CTL WRITE (WRN = 0) MR1, MR2 CSR CR THR ACR IMR CTUR CTLR
Counter/Timer (C/T)
The C/T operation is programmed by ACR[6:4]. One of eight timing sources can be used as the input to the C/T. The output of the C/T is available to the clock selectors and can be programmed by ACR[2:0} to be output on the MPO pin. In the timer mode, the C/T generates a square wave whose period is twice the number of clock periods loaded into the C/T upper and lower registers. The counter ready bit in the ISR is set once each cycle of the square wave. If the value in CTUR or CTLR is changed, the current half-period will not be affected, but subsequent half-periods will be affected. In this mode the C/T runs continuously and does not recognize the stop counter command (the command only resets the counter ready bit in the ISR). Receipt of a start C/T command causes the counter to terminate the current timing cycle and to begin a new cycle using the values in CTUR and CTLR. In the counter mode, the C/T counts down the number of pulses loaded into CTUR and CTLR. Counting begins upon receipt of a start C/T command. Upon reaching terminal count, the counter ready bit in the ISR is set. The counter continues counting past the terminal count until stopped by the CPU. If MPO is programmed to be the output of the C/T, the output remains high until terminal count is reached, at which time it goes low. The output returns to the high state and the counter ready bit is cleared when the counter is stopped by a stop counter command. the CPU may change the
NOTE; *Reserved registers should never be read during operation since they are reserved for internal diagnostics. ACR = Auxiliary control register CR = Command register CSR = Clock select register CTL = Counter/timer lower output register CTLR = Counter/timer lower preset register CTU = Counter/timer upper output register CTUR = Counter/timer upper preset register MR = Mode register A SR = Status register THR = Tx holding register * See Table 6 for BRG Test frequencies in this data sheet, and "Extended baud rates for SCN2681, SCN68681, SCC2691, 1998 Sep 04 7
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
values of CTUR and CTLR at any time, but the new count becomes effective only on the next start counter command following a stop counter command. If new values have not been loaded, the previous count values are preserved and used for the next count cycle. In the counter mode, the current value of the upper and lower eight bits of the counter may be read by the CPU. It is recommended that the counter be stopped when reading to prevent potential problems which may occur if a carry from the lower eight bits to the upper eight bits occurs between the times that both halves of the counter are read. However, a subsequent start counter command causes the counter to begin a new count cycle using the values in CTUR and CTLR. See further description in CTUR/CTLR section.
one-half of the bit period after the stop bit was sampled, then the receiver operates as if a new start bit transition had been detected at that point(one-half bit time after the stop bit was sampled). The parity error, framing error and overrun error (if any) are strobed into the SR at the received character boundary, before the RxRDY status bit is set. If a break condition is detected (RxD is low for the entire character including the stop bit), only one character consisting of all zeros will be loaded in the FIFO and the received SR break bit is set to 1. The RxD input must return to high for two (2) clock edges of the X1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. This will usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock.
Receiver and Transmitter
The UART is a full-duplex asynchronous receiver/transmitter. The operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter/timer, or from an external input. Registers associated with the communications channel are: the mode registers (MR1 and MR2), the clock select register (CSR), the command register (CR), the status register (SR), the transmit holding register (THR), and the receive holding register (RHR). Transmitter The transmitter accepts parallel data from the CPU and converts it to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the THR, the TxD output remains high and the TxEMT bit in the SR will be set to 1. Transmission resumes and the TxEMT bit is cleared when the CPU loads a new character in the THR. In the 16X clock mode, this also resynchronizes the internal 1X transmitter clock so that transmission of the new character begins with minimum delay. The transmitter can be forced to send a break (continuous low condition) by issuing a start break command via the CR. The break is terminated by a stop break command. If the transmitter is disabled, it continues operating until the character currently being transmitted and the character in the THR, if any, are completely sent out. Characters cannot be loaded in the THR while the transmitter is disabled. Receiver The receiver accepts serial data on the RxD pin, converts the serial input to parallel format, checks for start bit, stop bit, parity bit (if any), or break condition, and presents the assembled character to the CPU. The receiver looks for a high-to-low (mark-to-space) transition of the start bit on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled again each 16X clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of the bit time clock (1X clock mode). If RxD is sampled high, the start bit is invalid and the search for a valid start bit begins again. If RxD is still low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the proper number of data bits and the parity bit (if any) have been assembled, and one sop bit has been detected. The data is then transferred to the RHR and the RxRDY bit in the SR is set to a 1. If the character length is less than eight bits, the most significant unused bits in the RHR are set to zero. After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received without a stop bit (i.e. framing error) and RxD remains low for 1998 Sep 04 8
RECEIVER FIFO
The RHR consists of a first-in-first-out (FIFO) queue with a capacity of three characters. Data is loaded from the receive shift register into the top-most empty position of the FIFO. The RxRDY bit in the status register (SR) is set whenever one or more characters are available to be read, and a FFULL status bit is set if all three queue positions are filled with data. Either of these bits can be selected to cause an interrupt. A read of the RHR outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its associated status bits are `popped' thus emptying a FIFO position for new data.
Receiver Status Bits
In addition to the data word, three status bits (parity error, framing error, and received break) are appended to each data character in the FIFO. Status can be provided in two ways, as programmed by the error mode control bit in mode register 1. In the character mode, status is provided on a character-by-character basis: the status applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR for these three bits is the logical-OR of the status for all characters coming to the top of the FIFO since the last reset error command was issued. In either mode, reading the SR does not affect the FIFO. The FIFO is `popped' only when the RHR is read. Therefore, the SR should be read prior to reading the corresponding data character. The receiver can control the deactivation of RTS. If programmed to operate in this mode, the RTSN output will be negated when a valid start bit was received and the FIFO is full. When a FIFO position becomes available, the RTSN output will be re-asserted automatically. This feature can be used to prevent an overrun, in the receiver, by connecting the RTSN output to the CTSN input of the transmitting device.
Receiver Reset and Disable
Receiver disable stops the receiver immediately - data being assembled if the receiver shift register is lost. Data and status in the FIFO is preserved and may be read. A re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. A receiver reset will discard the present shift register data, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of the FIFO and re-align the FIFO read/write pointers. This has the appearance of "clearing or flushing" the receiver FIFO. In fact, the FIFO is NEVER cleared! The data in the FIFO remains valid until overwritten by another received character. Because of this, erroneous reading or extra reads of the receiver FIFO will miss-align the FIFO pointers and result in the reading of previously read data. A receiver reset will re-align the pointers.
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
In addition to the normal transmitter and receiver operation described above, the UART incorporates a special mode which provides automatic wake-up of the receiver through address frame recognition for multi-processor communications. This mode is selected by programming bits MR1[4:3] to `11'. In this mode of operation, a `master' station transmits an address character followed by data characters for the addressed `slave' station. The slave stations, whose receivers are normally disabled, examine the received data stream and `wake-up' the CPU [by setting RxRDY) only upon receipt of an address character. The CPU compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again. A transmitted character consists of a start bit, the programmed number of data bits, an address/data (A/D) bit, and the programmed number of stop bits. The polarity of the transmitted A/D bit is selected by the CPU by programming bit MR1[2]. MR1[2] = 0 transmits a zero in the A/D bit position which identifies the corresponding data bits as data, while MR1[2] = 1 transmits a one in the A/D bit position which identifies the corresponding data bits as an address. The CPU should program the mode register prior to loading the corresponding data bits in the THR. While in this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character in the RHR FIFO if the received A/D bit is a one, but discards the received character if the received A/D bit is a zero. If enabled, all received characters are then transferred to the CPU via the RHR. In either case, the data bits are loaded in the data FIFO while the A/D bit is loaded in the status FIFO position normally used for parity error (SR[5]). Framing error, overrun error, and break detect operate normally whether or not the receiver is enabled.
MULT-PURPOSE OUTPUT PIN
This pin can be programmed to serve as a request-to-send output, the counter/timer output, the output for the 1X or 16X transmitter or receiver clocks, the TxRDY output or the RxRDY/FFULL output (see ACR[2:0] - MPO Output Select). Please note that this pin drives both high and low. HOWEVER when it is programmed to represent interrupt type functions (such as receiver ready, transmitter ready or counter/timer ready) it will be switched to an open drain configuration in which case an external pull-up device would be required.
REGISTERS
The operation of the UART is programmed by writing control words in the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. Addressing of the registers is as described in Table 1. The contents of certain control registers are initialized to zero on reset (see RESET pin description). Care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems. For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. The contents of the MR, the CSR, and the ACR should only be changed while the receiver and transmitter are disabled, and certain changes to the ACR should only be made while the C/T is stopped. The bit formats of the UART are shown in Table 2.
MR1 - Mode Register 1
MR1 is accessed when the MR pointer points to MR1. The pointer is set to MR1 by RESET or by a set pointer command applied via the CR. After reading or writing MR1, the pointers are set at MR2. MR1[7] - Receiver Request-to-Send Control The bit controls the deactivation of the RTSN output (MPO) by the receiver. This output is normally asserted and negated by commands applied via the command register. MR1[7] = 1 causes RTSN to be automatically negated upon receipt of a valid start bit if the receiver FIFO is full. RTSN is reasserted when an empty FIFO position is available. This feature can be used to prevent overrun in the receiver by using the RTSN output signal to control the CTS input of the transmitting device. MR1[6] - Receiver Interrupt Select This bit selects either the receiver ready status (RxRDY) or the FIFO full status (FFULL) to be used for CPU interrupts. MR1[5] - Error Mode Select This bit selects the operating mode of the three FIFOed status bits (FE, PE, received break). In the character mode, status is provided on a character-by-character basis. The status applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last reset error command was issued. MR1[4:3] - Parity Mode Select If with parity or force parity is selected, a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data. MR![4:3] = 11 selects the channel to operate in the special wake-up mode. MR1[2] - Parity Type Select This bit selects the parity type (odd or even) if the with parity mode is programmed by MR1[4:3], and the polarity of the forced parity bit if the force parity mode is programmed. It has no effect if the no
MULTI-PURPOSE INPUT PIN
The MPI pin can be programmed as an input to one of several UART circuits. The function of the pin is selected by programming the appropriate control register (MR2[4]), ACR[6:4], CSR [7:4, 3:0]}. Only one of the functions may be selected at any given time. If CTS or GPI is selected, a change of state detector provided with the pin is activated. A high-to-low or low-to-high transition of the inputs lasting longer than 25-50s sets the MPI change-of-state bit in the interrupt status register. The bit is cleared via a command. The change-of-state can be programmed to generate an interrupt to the CPU by setting the corresponding bit in the interrupt mask register. The input port pulse detection circuitry uses a 38.4kHz sampling clock derived from one of the baud rate generator taps. This produces a sampling period of slightly more than 25s (assuming a 3.6864MHz oscillator input). The detection circuitry, in order to guarantee that a true change in level has occurred, requires two successive samples at the new logic level be observed. As a consequence, the minimum duration of the signal change is 25s if the transition occurs coincident with the first sample pulse. The 50s time refers to the condition where the change of state is just missed and the first change of state is not detected until after an additional 25s. The MPI pin has a small pull-up device that will source 1 to 4 mA of current from VCC. This pin does not require pull-up devices or VCC connection if it is not used.
1998 Sep 04
9
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
parity mode is programmed. In the special wake-up mode, it selects the polarity of the transmitted A/D bit. MR1[1:0] - Bits Per Character Select This field selects the number of data bits per character to be transmitted and received. The character length does not include the start, parity, and stop bits.
immediately. An exception to this is switching out of auto-echo or remote loopback modes; if the deselection occurs just after the receiver has sampled the stop bit (indicated in auto-echo by assertion o fRxRDY), and the transmitter is enabled, the transmitter is enabled, the transmitter will remain in auto-echo mode until one full stop bit has been retransmitted. MR2[5] - Transmitter Request-to-Send Control CAUTION: When the transmitter controls the OP pin (usually used for the RTSN signal) the meaning of the pin is not RTSN at all! Rather, it signals that the transmitter has finished the transmission (i.e., end of block). This bit allows deactivation of the RTSN output by the transmitter. This output is manually asserted and negated by the appropriate commands issued via the command register. MR2[5] set to 1 caused the RTSN to be reset automatically one bit time after the character(s) in the transmit shift register and in the THR (if any) are completely transmitted (including the programmed number of stop bits) if a previously issued transmitter disable is pending. This feature can be used to automatically terminate the transmission as follows: 1. Program the auto-reset mode: MR2[5]=1 2. Enable transmitter, if not already enabled 3. Assert RTSN via command 4. Send message 5. After the last character of the message is loaded to the THR, disable the transmitter. (If the transmitter is underrun, a special case exists. See note below.) 6. The last character will be transmitted and the RTSN will be reset one bit time after the last stop bit is sent. NOTE: The transmitter is in an underrun condition when both the TxRDY and the TxEMT bits are set. This condition also exists immediately after the transmitter is enabled from the disabled or reset state. When using the above procedure with the transmitter in the underrun condition, the issuing of the transmitter disable must be delayed from the loading of a single, or last, character until the TxRDY becomes active again after the character is loaded. MR2[4] - Clear-to-Send Control The sate of this bit determines if the CTSN input (MPI) controls the operation of the transmitter. If this bit is 0, CTSN has no effect on the transmitter. If this bit is a 1, the transmitter checks the sate of CTSN each time it is ready to send a character. If it is asserted (low), the character is transmitted. If it is negated (high), the TxD output remains in the marking state and the transmission is delayed until CTSN goes low. Changes in CTSN while a character is being transmitted do not affect the transmission of that character. This feature can be used to prevent overrun of a remote receiver. MR2[3:0] - Stop Bit Length Select This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character length of 5 bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. In all cases, the receiver only checks for a mark condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled). If an external 1X clock is used for the transmitter, MR2[3] = 0 selects one stop bit and MR2[3] = 1 selects two stop bits to be transmitted.
MR2 - Mode Register 2
MR2 is accessed when the channel MR pointer points to MR2, which occurs after any access to MR1. Accesses to MR2 do not change the pointer. MR2[7:6] - Mode Select The UART can operate in one of four modes. MR2[7:6] = 00 is the normal mode, with the transmitter and receiver operating independently. MR2[7:6] = 01 places the channel in the automatic echo mode, which automatically re-transmits the received data. The following conditions are true while in automatic echo mode: 1. Received data is re-clocked and retransmitted on the TxD output. 2. The receive clock is used for the transmitter. 3. The receiver must be enabled, but the transmitter need not be enabled. 4. The TxRDY and TxEMT status bits are inactive. 5. The received parity is checked, but is not regenerated for transmission, i.e., transmitted parity bit is as received. 6. Character framing is checked, but the stop bits are retransmitted as received. 7. A received break is echoed as received until the next valid start bit is detected. 8. CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. Two diagnostic modes can also be selected. MR2[7:6] = 10 selects local loopback mode. In this mode: 1. The transmitter output is internally connected to the receiver input. 2. The transmit clock is used for the receiver. 3. The TxD output is held high. 4. The RxD input is ignored. 5. The transmitter must be enabled, but the receiver need not be enabled. 6. CPU to transmitter and receiver communications continue normally. The second diagnostic mode is the remote loopback mode, selected by MR2[7:6] = 11. In this mode: 1. Received data is re-clocked and retransmitted on the TxD output. 2. The receive clock is used for the transmitter. 3. Received data is not sent to the local CPU, and the error status conditions are inactive. 4. The received parity is not checked and is not regenerated for transmission, i.e., the transmitted parity bit is as received. 5. The receiver must be enabled, but the transmitter need not be enabled. 6. Character framing is not checked, and the stop bits are retransmitted as received. 7. A received break is echoed as received until the next valid start bit is detected. When switching in and out of the various modes, the selected mode is activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. Likewise, if a mode is deselected, the device will switch out of the mode
1998 Sep 04
10
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
Table 2.
Register Bit Formats
Bit 5
Error Mode* 0 = Char 1 = Block
Bit 7 Bit 6 MR1 (Mode Register 1)
RxRTS Control 0 = no 1 = yes RxINT Select 0 = RxRDY 1 = FFULL
Bit 4
Bit 3
Bit 2
Parity Type 0 = Even 1 = Odd
Bit 1
Bit 0
Parity Mode 00 = With parity 01 = Force parity 10 = No parity 11 = Special mode
Bits per Character 00 = 5 01 = 6 10 = 7 11 = 8
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2) Channel Mode
00 = Normal 01 = Auto echo 10 = Local loop 11 = Remote loop
TxRTS Control
0 = No 1 = Yes
CTS Enable Tx
0 = No 1 = Yes 0 = 0.563 1 = 0.625 2 = 0.688 3 = 0.750
Stop Bit Length*
4 = 0.813 5 = 0.875 6 = 0.938 7 = 1.000 8 =1.563 9 = 1.625 A = 1.688 B = 1.750 C = 1.813 D = 1.875 E = 1.938 F = 2.000
NOTE: *Add 0.5 to values shown for 0-7 if channel is programmed for 5 bits/character.
CSR (Clock Select Register)
Receiver Clock Select See Text Transmitter Clock Select See Text
See Table 6 for BRG Test frequencies in this data sheet, and "Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B" Philips Semiconductors ICs for Data Communications, IC-19, 1994.
CR (Command Register)
Miscellaneous Commands See Text Disable Tx 0 = No 1 = Yes Enable Tx 0 = No 1 = Yes Disable Rx 0 = No 1 = Yes Enable Rx 0 = No 1 = Yes
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
SR (Channel Status Register)
Received Break 0 = No 1 = Yes * Framing Error 0 = No 1 = Yes * Parity Error 0 = No 1 = Yes * Overrun Error 0 = No 1 = Yes TxEMT 0 = No 1 = Yes TxRDY 0 = No 1 = Yes FFULL 0 = No 1 = Yes RxRDY 0 = No 1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these bits [7:5] from the top of the FIFO together with bits [4;0]. These bits are cleared by a reset error status command. In character mode they are reset when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
ACR (Auxiliary Control Register)
BRG Set Select 0 = Set 1 1 = Set 2 Counter/Timer Mode and Source See Text Power-Down Mode 0 = On PWRDN Active 1 = Off Normal MPO Pin Function Select 000 = RTSN 001 = C/TO 010 = TxC (1X) 011 = TxC (16X) 100 = RxC (1X) 101 = RxC (16X) 110 = TxRDY 111 = RxRDY/FFULL
ISR (Interrupt Status Register)
MPI Pin Change 0 = No 1 = Yes MPI Pin Current State 0 = Low 1 = High Not used Counter Ready 0 = No 1 = Yes Delta Break 0 = No 1 = Yes RxRDY/ FFULL 0 = No 1 = Yes TxEMT 0 = No 1 = Yes TxRDY 0 = No 1 = Yes
IMR (Interrupt Mask Resister)
MPI Change Interrupt 0 = Off 1 = On MPI Level Interrupt 0 = Off 1 = On Not used Counter Ready Int 0 = Off 1 = On Delta Break Interrupt 0 = Off 1 = On RxRDY/FFULL Interrupt 0 = Off 1 = On TxEMT Interrupt 0 = Off 1 = On TxRDY Interrupt 0 = Off 1 = On
1998 Sep 04
11
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
Table 2. Register Bit Formats (Continued)
CTUR (Counter/Timer Upper Register)
C/T[15] C/T[14] C/T[13] C/T[12] C/T[11] C/T[10] C/T[9] C/T[8]
Bit 7
C/T[7]
Bit 6
C/T[6]
Bit 5
C/T[5]
Bit 4
C/T[4]
Bit 3
C/T[3]
Bit 2
C/T[2]
Bit 1
C/T[1]
Bit 0
C/T[0]
CTLR (Counter/Timer Lower Register)
CSR - Clock Select Register (see Table 6. also) Table 3. Baud Rate Selection
CSR[3:0]/ [7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ACR[7] = 0 50 110 134.5 200 300 600 1,200 1,050 2,400 4,800 7,200 9,600 38.4k Timer MPI - 16X MPI-1X ACR[7] = 1 75 110 134.5 150 300 600 1,200 2,000 2,400 4,800 1,800 9,600 19.2k Timer MPI - 16X MPI-1X
The receiver clock is always a 16X clock, except for CSR[7:4] = 1111. See "Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B" in application notes elsewhere in this publication CSR[7:4] - Receiver Clock Select This field selects the baud rate clock for the receiver as shown in Table 3. The baud rates listed are for a 3.6864MHz crystal or external clock. CSR[3:0] - Transmitter Clock Select This field selects the baud rate clock for the transmitter. The field definition is as shown in Table 3.
CR - Command Register
CR is used to write commands to the UART. Multiple commands can be specified in a single write to CR as long as the commands are non-conflicting, e.g., the enable transmitter and reset transmitter commands cannot be specified in a single command word. CR[7:4] - Miscellaneous Commands The encoded value of this field may be used to specify a single command as follows: NOTE: Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. 0000 No command. 0001 Reset MR pointer. Causes the MR pointer to point to MR1. 0010 Reset receiver. Resets the receiver as if a hardware reset had been applied. The receiver is disable and the FIFO is flushed.
0011 Reset transmitter. Resets the transmitter as if a hardware reset had been applied 0100 Reset error status. Clears the received break, parity error, framing error, and overrun error bits in the status register (SR[7:4]}. Used in character mode to clear OE status (although RB, PE, and FE bits will also be cleared), and in block mode to clear all error status after a block of data has been received. 0101 Reset break change interrupt. Causes the break detect change bit in the interrupt status register (ISR[3]) to be cleared to zero. 0110 Start break. Forces the TxD output low (spacing). If the transmitter is empty, the start of the break condition will be delayed up to two bit times. If the transmitter is active, the break begins when transmission of the character is completed. If a character is in the THR, the start of break is delayed until that character or any others loaded after it have been transmitted (TxEMT must be true before break begins). The transmitter must be enabled to start a break 0111 Stop break. The TxD line will go high (marking) within two bit times. TxD will remain high for one bit time before the next character, if any, is transmitted. 1000 Start C/T. In counter or timer modes, causes the contents of CTUR/CTLR to be preset into the counter/timer and starts the counting cycle. In timer mode, any counting cycle in progress when the command is issued is terminated. In counter mode, has no effect unless a stop C/T command was issued previously. 1001 Stop counter. In counter mode, stops operation of the counter/timer, resets the counter ready bit in the ISR, and forces the MPO output high if it is programmed to be the output of the C/T. In timer mode, resets the counter ready bit in the ISR but has no effect on the counter/timer itself or on the MPO output. 1010 Assert RTSN. Causes the RTSN output (MPO) to be asserted (low). 1011 Negate RTSN.Causes the RTSN output (MPO) to be negated (high). 1100 Reset MPI change interrupt. Causes the MPI change bit in the interrupt status register (ISR[7]) to be cleared to zero. 1100 Reserved. 111x Reserved. CR[3] - Disable Transmitter This command terminates operation and resets the TxRDY and TxEMT status bits. However, if a character is being transmitted or if a character is in the THR when the transmitter is disabled, the transmission of the character(s) is completed before assuming the inactive state. A disabled transmitter cannot be loaded. CR[2] - Enable Transmitter Enables operation of the channel A transmitter. The TxRDY status bit will be asserted.
1998 Sep 04
12
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
CR[1] - Disable Receiver This command terminates operation of the receiver immediately; a character being received will be lost. The command has no effect on the receiver status bits or any other control registers. If the special wake-up mode is programmed, the receiver operates even if it is disabled (see Wake-up Mode). CR[0] - Enable Receiver Enables operation of the receiver. If not in the special wake-up mode, this also forces the receiver into the search for start bit state.
SR[2] - Transmitter Ready (TxRDY) This bit, when set, indicates that the THR is empty and ready to be loaded with a character. This bit is cleared when the THR is loaded by the CPU and is set when the character is transferred to the transmit shift register. TxRDY is reset when the transmitter is disabled and is set when the transmitter is first enabled, e.g., characters loaded in the THR while the transmitter is disabled will not be transmitted. SR[1] - FIFO Full (FFULL) This bit is set when a character is transferred from the receive shift register to the receive FIFO and the transfer causes the FIFO to become full, i.e., all three FIFO positions are occupied. It is reset when the CPU reads the FIFO and there is no character in the receive shift register. If a character is waiting in the receive shift register because the FIFO is full, FFULL will be reset by the CPU read and then set by the transfer of the character to the FIFO, which causes all three FIFO positions to be occupied. SR[0] - Receiver Ready (RxRDY) This bit indicates that a character has been received and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the RHR, and no more characters are in the FIFO.
SR - Channel Status Register
The status register is updated while RDN is negated. Therefore, the bus interface used with this device must not use a static RDN line. The RDN line must be pulsed to allow status register updates. SR[7] - Received Break This bit indicates that an all zero character of the programmed length has been received without a stop bit. Only a single FIFO position is occupied when a break is received; further entries to the FIFO are inhibited until the RxD line returns to the marking state for at least one half bit time two successive edges of the internal or external 1X clock. This will usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. When this bit is set, the change in break bit in the ISR (ISR[3]) is set. ISR[3] is also set when the end of the break condition, as defined above, is detected. The break detect circuitry is capable of detecting breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must last until the end of the next character time in order for it to be detected. SR[6] - Framing Error (FE) This bit, when set, indicates that a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. SR[5]- Parity Error (PE) This bit is set when the with parity or force parity mode is programmed and the corresponding character in the FIFO was received with incorrect parity. In special wake-up mode, the parity error bit stores the received A/D bit. SR[4] - Overrun Error (OE) This bit, when set, indicates that one or more characters in the received data stream have been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. This bit is cleared by a reset error status command. SR[3] - Transmitter Empty (TxEMT) This bit will be set when the transmitter underruns, i.e., both the TxEMT and TxRDY bits are set. This bit and TxRDY are set when the transmitter is first enabled and at any time it is re-enabled after either (a) reset, or (b) the transmitter has assumed the disabled state. It is always set after transmission of the last stop bit of a character if no character is in the THR awaiting transmission. It is reset when the THR is loaded by the CPU, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the underrun condition.
ACR - Auxiliary Control Register
ACR[7] - Baud Rate Generator Set Select This bit selects one of two sets of baud rates generated by the BRG. Set 1: Set 2: 50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k, and 38.4k baud. 75, 110, 134.5, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k, 9.6k, and 19.2k baud.
The selected set of rates is available for use by the receiver and transmitter. See Table 3 for characteristics of the BRG. ACR[6:4] - Counter/Timer Mode and Clock Source Select This field selects the operating mode of the counter/timer and its clock source as follows:
Table 4.
ACR [6:4] 000 001 010 011 100 101 110 111
ACR[6:4] Operating Mode
Mode Counter Counter Counter Counter Timer (square wave) Timer (square wave) Timer (square wave) Timer (square wave) Clock Source MPI pin MPI pin divided by 16 TxC-1X clock transmitter of the
Crystal or X1/CLK divided by 16 MPI pin MPI pin divided by 16 Crystal or external clock (X1/CLK) Crystal or X1/CLK divided by 16
The timer mode generates a squarewave. ACR[3] - Power-Down Mode Select This bit, when set to zero, selects the power-down mode. In this mode, the SCC2691 oscillator is stopped and all functions requiring this clock are suspended. The contents of all registers are saved. It is recommended that the transmitter and receiver be disabled prior
1998 Sep 04
13
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
to placing the SCC2691 in this mode. Note that this bit must be set to a logic 1 after reset. When the power-down mode is enabled, internal circuitry forces the X1/CLK pin to the low state and the X2 pin to the high state. If an external clock is being used to drive the device, it is recommended that the clock source be three-stated or forced low while the UART is in power-down mode in order to prevent the clock driver from being short circuited.
011 100
The 16X clock for the transmitter. This is the clock selected by CSR[3:0] = 1111. The 1X clock for the receiver, which is the clock that samples the received data. If data is not being received, a non-synchronized 1X clock is output. The 16X clock for the receiver. This is the clock selected by CSR[7:4], and is a 1X clock if CSR[7:4] = 1111. The transmitter register empty signal, which is the complement of SR[2]. Active low output. The receiver ready or FIFO full signal (complement of ISR[2]). Active-low output.
101 110 111
Table 5.
BRG Characteristics
Actual 16X Clock (kHz) 0.8 1.2 1.759 2.153 2.4 3.2 4.8 9.6 16.756 19.2 28.8 32.056 38.4 76.8 115.2 153.6 230.4 307.2 460.8 614.4 921.6 1843.2K Error (%) 0 0 -0.069 0.059 0 0 0 0 -0.260 0 0 0.175 0 0 0 0 0 0 0 0 0 0
Nom Rate (Baud) 50 75 110 134.5 150 200 300 600 1050 1200 1800 2000 2400 4800 7200 9600 14.4K 19.2k 28.8K 38.4k 57.6K 115.2K
ISR - Interrupt Status Register
This register provides the status of all potential interrupt sources. The contents of this register are masked by the interrupt mask register (IMR). If a bit in the ISR is a `1' and the corresponding bit in the IMR is also a `1', the INTRN output is asserted (low). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR; the true status is provided regardless of the contents of the IMR. This register is cleared when the device is reset. ISR[7] - MPI Change-of-State This bit is set when a change-of-state occurs at the MPI input pin. It is reset by a reset change interrupt command. ISR[6] - MPI Current State This bit provides the current state of the MPI pin. This information is latched and reflects the state of the pin at the leading edge of the ISR ready cycle. ISR[4] - Counter Ready In the counter mode of operation, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated square wave (every other time the C/T reaches zero count). The bit is reset by a stop counter command. The command, however, does not stop the C/T. ISR[3] - Change in Break This bit, when set, indicates that the receiver has detected the beginning or end of a received break. It is reset when the CPU issues a reset break change interrupt command. ISR[2] - Receiver Ready or FIFO Full The function of this bit is programmed by MR1[6]. If programmed as receiver ready, it indicates that a character has been received and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the receiver FIFO. If the FIFO contains more characters, the bit will be set again after the FIFO is read. If programmed as FIFO full, it is set when a character is transferred from the receive holding register to the receive FIFO and the transfer causes the FIFO to become full, i.e., all three FIFO positions are occupied. It is reset when the FIFO is read and there is no character in the receive shift register. If there is a character waiting in the receive shift register because the FIFO is full, the bit is set again when the waiting character is transferred into the FIFO. ISR[1] - Transmitter Empty This bit is a duplicate of TxEMT (SR[3]). ISR[0] - Transmitter Ready This bit is a duplicate of TxRDY (SR[2]).
Duty cycle of 16X clock is 50% 1%. Crystal or Clock = 3.6864MHz Asynchronous UART communications can tolerate frequency error of 4.1% to 6.7% in a "clean" communications channel. The percent of error changes as the character length changes. The above percentages range from 5 bits not parity to 8 bits with parity and one stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a stop bit length of 9/16 is used, the error tolerance will approach 0 due to a variable error of up to 1/16 bit time in receiver clock phase alignment to the start bit. ACR[2:0] - MPO Output Select This field programs the MPO output pin to provide one of the following: 000 Request-to-send active-low output (RTSN). This output is asserted and negated via the command register. RTSN can be programmed to be automatically reset after the character in the transmitter is completely shifted out or when the receiver FIFO and receiver shift register are full using MR2[5] and MR1[7], respectively. 001 The counter/timer output. In the timer mode, this output is a square wave with a period of twice the value (in clock periods) of the contents of the CTUR and CTLR. In the counter mode, the output remains high until the terminal count is reached, at which time it goes low. The output returns to the high state when the counter is stopped by a stop counter command. 010 The 1X clock for the transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a non-synchronized 1X clock is output.
1998 Sep 04
14
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
IMR - Interrupt Mask Register
The programming of this register selects which bits in the ISR cause an interrupt output. If a bit in the ISR is a `1' and the corresponding bit in the IMR is a `1', the INTRN output is asserted (low). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask reading of the ISR. NOTE: When IMR[6] is a 1, a 1 on the MPI pin causes and interrupt.
0.3/26.3 which is 1.14%; well within the ability asynchronous mode of operation. If the value in CTUR or CTLR is changed, the current half-period will not be affected, but subsequent half-periods will be. The counter ready status bit (ISR[4]) is set once each cycle of the square wave. The bit is reset by a stop counter command. The command, however, does not stop the C/T. The generated square wave is output on MPO if it is programmed to be the C/T output. In the counter mode, the C/T counts down the number of pulses loaded in CTUR and CTLR. Counting begins upon receipt of a start C/T command. Upon reaching the terminal count, the counter ready interrupt bit (ISR[4]) is set. the counter continues counting past the terminal count until stopped by the CPU. If MPO is programmed to be the output of the C/T, the output remains high until the terminal count is reached, at which time it goes low. The output returns to the high state and ISR[4] is cleared when the counter is stopped by a stop counter command. The CPU may change the values of CTUR and CTLR at any time, but the new count becomes effective only on the next start counter command. If new values have not been loaded, the previous values are preserved and used for the next count cycle.
CTUR and CTLR - Counter/Timer Registers
The CTUR and CTLR hold the eight MSBs and eight LSBs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. The minimum value which may be loaded is H`0002'. In the timer (programmable divider) mode, the C/T generates a square wave whose period is twice the value (in clock periods) of the CTUR and CTLR. The waveform so generated is often used for a data clock. The formula for calculating the divisor n to load to the CTUR and CTLR for a particular 1X data clock is shown below: n+ C T Clock Frequency 2 x 16 x Baud rate desired
Often this division will result in a non-integer number; 26.3, for example. One can only program integer numbers in a digital divider. Therefore, 26 would be chosen. This gives a baud rate error of
RESET tRES
SD00028
Figure 3. Reset Timing
A0-A2
tAS
CEN
tAH tCS tCH tRWD
tRW
RDN
tDD
D0-D7 (READ) FLOAT NOT VALID VALID
tDF
FLOAT
tRWD
WRN
tDS
D0-D7 (WRITE) VALID
tDH
SD00124
Figure 4. Bus Timing
1998 Sep 04
15
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
RDN
tPS
MPI
tPH
WRN
tPD
MPO
SD00125
Figure 5. I/O Timing
WRN
VM tIR VOL +0.5V VOL
INTERRUPT 1 OUTPUT
RDN INTERRUPT 1 OUTPUT
tIR
VOL +0.5V VOL
NOTES: 1. INTRN or MPO when used as interrupt outputs. 2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. SD00126
Figure 6. Interrupt Timing
tCLK tCTC tRx tTx
X1/CLK C/T CLK RxC TxC DRIVING FROM EXTERNAL SOURCE CLK 5V
Y1 = 3.6864MHz, CL = 20pF C1 = C2 = 24pF X1/CLK
C1
tCLK tCTC tRx tTx
Y1 C2
50k to 150k
SCC2691
X2 470 X1 N/C X2 TYPICAL CRYSTAL SPECIFICATION FREQUENCY. . . . . . . . . . . . . . 2-4MHz LOAD CAPACITANCE (CL). . . 20 or 32pF (typical) TYPE OF OPERATION . . . . . .PARALLEL RESONANT, FUND. MODE
SD00127
Figure 7. Clock Timing
1998 Sep 04
16
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
TxC (INPUT)
1 BIT TIME (1 OR 16 CLOCKS)
tTXD
TxD
tTCS TxC (1X OUTPUT)
SD00092
Figure 8. Transmit Timing
RxC (1X INPUT)
tRXS
tRXH
RxD
SD00093
Figure 9. Receive Timing
1998 Sep 04
17
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
TxD
D1
D2
D3
BREAK
D4
D6
TRANSMITTER ENABLED
TxRDY (SR2)
WRN D1 D2 D3 START BREAK D4 STOP BREAK D5 WILL NOT BE TRANSMITTED D6
CTSN1 (MPI)
RTSN2 (MPO) CR[7:4] = 1010 NOTES: 1. TIMING SHOWN FOR MR2[4] = 1. 2. TIMING SHOWN FOR MR2[5] = 1. CR[7:4] = 1010
SD00128
Figure 10. Transmitter Timing
RxD RECEIVER ENABLED
D1
D2
D3
D4
D5
D6
D7
D8
RxRDY (SR0) D2 FFULL (SR1)
RxRDY/ FFULL MPO2
RDN S OVERRRUN (SR4) D1 D
S = STATUS D = DATA D5 WILL BE LOST
S
D D2
S
D D3
S
D D4 RESET BY COMMAND
RTS1 MPO MPO = 1 (CR[7:4] = 1010) NOTES; 1. Timing shown for MR1[7]. 2. Shown for ACR[2:] = 111 and MR1[6] = 0.
SD00129
Figure 11. Receiver Timing 1998 Sep 04 18
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
MASTER STATION TxD TRANSMITTER ENABLED ADD#1
BIT 9 1 D0
BIT 9 0
BIT 9 ADD#2 1
TxRDY (SR2)
CSN (WRITE] MR1[4:3] = 11 ADD#1 MR1[2] = 0 D0 MR1[2] = 1 PERIPHERAL STATION BIT 9 RxD 0 ADD#1 BIT 9 1 D0 0 BIT 9 ADD#2 BIT 9 1 BIT 9 0 MR1[2] = 1 ADD#2
RECEIVER ENABLED
RxRDY (SR0)
RDN/WRN MR1[4:3] = 11 ADD#1 S D0 D
S = STATUS D = DATA
S ADD#2
D
SD00130
Figure 12. Wake-Up Mode
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. The CTS input is on pin MPI. The CTS signal is active low; thus, it is called CTSN. RTS is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. It is also active low and is, thus, called RTSN. RTSN is on pin MP0. A receiver's RTS output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say that RTS and CTS are different ends of the same wire! MR2(4) is the bit that allows the transmitter to be controlled by the CTS pin (MPI). When this bit is set to one AND the CTS input is driven high, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of the receiver that will be connected to the transmitter's CTS input. The receiver will set RTS high when the receiver FIFO is full AND the start bit of the fourth character is sensed. Transmission then stops with four valid characters in the receiver. When MR2(4) is set to one, CTSN must be at zero for the transmitter to operate. If MR2(4) is set to zero, the MP pin will have no effect on the operation of the transmitter. MR1(7) is the bit that allows the receiver to control MP0. When MP0 is controlled by the receiver, the meaning of that pin will be RTS. However, a point of confusion arises in that MP0 may also be controlled by the transmitter. When the transmitter is controlling this pin, its meaning is not RTS at all. It is, rather, that the transmitter has finished sending its last data byte. Programming the MP0 pin to be controlled by the receiver and the transmitter at the same time is allowed, but would usually be incompatible. 1998 Sep 04 19
RTS can also be controlled by the commands 1010 and 1011 in the command register. RTS is expressed at the MP0 pin which is still an output port. Therefore, the state of MP0 should be set low (by commands to the CR register) for the receiver to generate the proper RTS signal. The logic at the output is basically a NAND of the MP0 bit register and the RTS signal as generated by the receiver. When the RTS flow control is selected via the MR(7) bit the state of the MP0 register is not changed. Terminating the use of "Flow Control" (via the MR registers) will return the MP0 pin to the control of the MP0 register.
Transmitter Disable Note
The sequence of instructions enable transmitter -- load transmit holding register -- disable transmitter will result in nothing being sent if the time between the end of loading the transmit holding register and the disable command is less that 3/16 bit time in the 16x mode or one bit time in the 1x mode. Also, if the transmitter, while in the enabled state and underrun condition, is immediately disabled after a single character is loaded to the transmit holding register, that character will not be sent. In general, when it is desired to disable the transmitter before the last character is sent AND the TxEMT bit is set in the status register (TxEMT is always set if the transmitter has underrun or has just been enabled), be sure the TxRDY bit is active immediately before issuing the transmitter disable instruction. TxRDY sets at the end of the "start bit" time. It is during the start bit that the data in the transmit holding register is transferred to the transmit shift register. Non-standard baud rates are available as shown in Table 6 below, via the BRG Test function.
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
Table 6. Baud Rates Extended
Normal BRG CSR[7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ACR[7] = 0 50 110 134.5 200 300 600 1,200 1,050 2,400 4,800 7,200 9,600 38.4K Timer I/O2 - 16X I/O2 - 1X ACR[7] = 1 75 110 134.5 150 300 600 1,200 2,000 2,400 4,800 1,800 9,600 19.2K Timer I/O2 - 16X I/O2 - 1X ACR[7] = 0 4,800 880 1,076 19.2K 28.8K 57.6K 115.2K 1,050 57.6K 4,800 57.6K 9,600 38.4K Timer I/O2 - 16X I/O2 - 1X BRG Test ACR[7] = 1 7,200 880 1,076 14.4K 28.8K 57.6K 115.2K 2,000 57.6K 4,800 14.4K 9,600 19.2K Timer I/O2 - 16X I/O2 - 1X
NOTE: Each read on address H`2' will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This change affects all receivers and transmitters on the DUART. See "Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B" in application notes elsewhere in this publication. The test mode at address H`A' changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes. A condition that occurs infrequently has been observed where the receiver will ignore all data. It is caused by a corruption of the start bit generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to continue to function properly.
Reset in the Normal Mode (Receiver Enabled)
Recovery can be accomplished easily by issuing a receiver software reset followed by a receiver enable. All receiver data, status and programming will be preserved and available before reset. The reset will NOT affect the programming.
Reset in the Wake-Up Mode (MR1[4:3] = 11)
Recovery can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and available before reset. The reset will NOT affect the programming. The receiver has a digital filter designed to reject "noisy" data transitions and the receiver state machine was designed to reject noisy start bits or noise that might be considered a start bit. In spite of these precautions, corruption of the start bit can occur in 15ns window approximately 100ns prior to the rising edge of the data clock. The probability of this occurring is less than 10-5 at 9600 baud. A corrupted start bit may have some deleterious effects in ASYNC operation if it occurs within a normal data block. The receiver will tend to align its data clock to the next `0' bit in the data stream, thus potentially corrupting the remainder of the data block. A good design practice, in environments where start bit corruption is possible, is to monitor data quality (framing error, parity error, break change and received break) and "data stopped" time out periods. Time out periods can be enabled using the counter/timer in the SCC2691, SCC2692, SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem.
SD00097
1998 Sep 04
20
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
1998 Sep 04
21
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1998 Sep 04
22
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
1998 Sep 04
23
Philips Semiconductors
Product specification
Universal asynchronous receiver/transmitter (UART)
SCC2691
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 09-98 Document order number: 9397 750 04358
Philips Semiconductors
1998 Sep 04 24

▲Up To Search▲

Price & Availability of SCC2691

	To Download SCC2691 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .